SCAPE Journal Club

SCAPE Journal Club is a biweekly journal club to facilitate discussion and understanding the technical details of research in performance analysis & evaluation, power-aware computing, and other related system research area in high-end computing.   Each session, a technical paper is selected to be presented by one of the club members, and all the other members are required to have read the paper before the meeting.

When and where to meet  

The Journal club meets at 10:00-11:30 every other Friday from Sept. 1 at room 225 in Knowledge Work II building.

Club members

The current members include SCAPE faculties and graduate students. New members are always welcome, and are granted amnesty from both presenting and selecting papers for their first few weeks. The current organizer/keeper of the mailing list is Rong Ge. Send her email if you would like to join us!

Participation Required

During each meeting, the presenter will spend at most 15 minutes introducing the paper. Then Prof. Cameron will lead a discussion asking all participants to comment on questions related to the paper. Students are expected to participate in a number of ways: 1) It is expected participants will read the current paper PRIOR to attending the meeting - those who do not may be asked to no longer attend. 2) All students are encouraged (and will be randomly called upon) to participate in discussions - especially you quiet ones out there. 3) Lively discussions are encouraged, but collegial manners are expected and must be maintained at all times. 4) More senior students will be asked to present papers at future club meetings.

The tentative reading list for Fall 2006

Date Presenter Paper Area
Sept. 1 Rong Ge K. W. Cameron, R. Ge, X. H. Sun," lognP and log3P: Accurate Analytical Models of Point-to-Point Communication in Distributed Systems", to appear in IEEE Transactions on Computers Performance modeling and evaluation
Sept. 15 Xizhou Feng X. Feng, K. W. Cameron, D. Buell. "PBPI: a High Performance Implementation of Bayesian Phylogenetic Inference." SC 2006 Bioinformatics and high performance computing
Sep. 29 Rong Ge Kirk W. Cameron, Rong Ge, Xizhou Feng ,High-Performance, Power-Aware Distributed Computing for Scientific Applications, Computer, 2005 Power profiling and power aware computing
Oct. 13 Dong Li A. Varma, B. Ganesh, M. Sen, S. R. Choudhary, L. Srinivasan, and B. Jacob. "A Control-Theoretic Approach to Dynamic Voltage Scaling." CASES 2003 Power aware computing
Oct. 27 Leon Song Y. Li, D. Brooks, Z. Hu, and K.Skadron, "Performance,Energy, and Thermal Considerations for SMT and CMP Architectures," HPCA 2005. Thermal aware computing
Dec. 8 Hari Pyla T. Heath, A. Centeno, P. George, L. Ramos, Y. Jaluria, and R. Bianchini, "Mercury and Freon: Temperature Emulation and Management for Server Systems", ASPLOS 2006 Thermal and Temperature
Dec. 15     Network simulation
Jan. 5   TBD  

Prior reading list

Of course, the papers we have read most thoroughly are our own publications, see SCAPE publications. The following list doesn't include our own publications, and those with *** are recommended for new SCAPE members to read first in order to introduce them to SCAPE research area.

    Power-Conscious Computing

Intro material and tools

***1.  D. M. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. N. Kudva, A. Buyuktosunoglu, J.-D. Wellman, V. Zyuban, M. Gupta, and P. W. Cook, "Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors," IEEE Micro, 20 (6), pp. 26-44, 2000.

***2.  D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," in proceedings of 27th International Symposium on Computer Architecture, pp. P. 83-94, Vancouver, BC, 2000.

      3.  L. Benini, A. Bogliolo and G. De Micheli, "A Survey of Design Techniques for System-Level Dynamic Power Management,” IEEE Transactions on VLSI, 8(3), June 2000.

      4.  N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, W. Ye, and D. Duarte, “Evaluating Integrated Hardware-Software Optimizaitions Using a Unified Energy Estimation Framework,” IEEE Transactions on Computers, 52(1), pp 59-76, 2003.

      5.  H. Wang, X. Zhu, L. Peh, S. Malik, “Orion: A Power-performance Simulator for Interconnection Networks,” Proceedings of Micro-35, 2002.

Microarchitectures

      1.  B. Fields, R. Bodik, M. Hill, “Slack: Maximizing Performance Under Technological Constraints,” Proceedings of 29th International Symposium on Computer Architecture, 2002.

      2.  V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, F. Baez, “Reducing Power in High-Performance Microprocessors,” 35th Design Automation Conference, 1998.

      3.  R. Gonzalez and M. Horowitz, “Energy Dissipation in General Purpose Microprocessors,”IEEE Journal of Solid-State Circuits, 31(9), pp 1277-1284, 1996.

***4.  J. Lorch, and A. Smith, “Improving Dynamic Voltage Scaling Algorithms with PACE,” Proceedings of ACM SIGMETRICS 2001.

Systems

      1.  Y. Lu, L. Benini, G. Micheli, “Power-Aware Operating Systems for Interactive Systems,” IEEE Transactions on VLSI Systems, 10(2), April 2002.

***2.  H. Zeng, C. Ellis, A. Lebeck, and A. Vahdat, "ECOSystem: Managing Energy as a First-Class Operating System Resource," Proceedings of Proceedings of Architectural Support for Programming Languages and Operating Systems (ASPLOS X), pp. 123-32, San Jose, CA, 2002.

      3.  Lebeck, X. Fan, H. Zheng, C. Ellis, “Power-Aware Page Allocation,” ACM SIGOPS Operating Systems Review, 34(5), December 2000.

      4.  V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. Irwin, “Hardware and Software Techniques for Controlling DRAM Power Modes,” IEEE Transactions on Computers 50(11), November 2001.

      5.  Gniady, Y. C. Hu, and Y.-H. Lu, "Program Counter Based Techniques for Dynamic Power Management," in proceedings of International Symposium on High-Performance Computer Architecture (HPCA-10), Madrid, Spain, 2004.

Heat Dissipation

***1.  D. Brooks, M. Martonosi, “Dynamic Thermal Management for High-Performance Microprocessors,” Proceedings of the 7th International Symposium on High-Performance Computer Architecture, January 2001.

      2.  K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, “Temperature-aware Mircoarchitecture,” Proceedings of the 30th International Symposium on Computer Architecture, June 2003.

      3.  Andreas Weißel and Frank Bellosa, “Dynamic Thermal Management for Distributed Systems” Proceedings of the First Workshop on Temperature-Aware Computer Systems (TACS'04), Munich, Germany, June 20, 2004

      4.  T. Heath, A. P. Centeno, P. George, L. Ramos, Y. Jaluria, and R. Bianchini. "Mercury and Freon: Temperature Emulation and Management in Server Systems". Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006

General Propose and Distributed Systems

      1.  C. Hsu, W. Feng, "A Power-Aware Run-Time System for High-Performance Computing," Proceeding of IEEE/ACM Supercomputing 2005 (SC'05), November 2005

      2.  C. Hsu and W. Feng. "Effective dynamic Voltage Scaling through CPU-Boundedness Detection." Proceedings of 4th Workshop Power-Aware Computer Systems (PACS 04), Dec. 2004.

***3.  C-H. Hsu and U. Kremer, "The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction," ACM SIGPLAN Conference on Programming Languages, Design, and Implementation (PLDI'03), San Diego, CA, June 2003.

      4.  C-H. Hsu and U. Kremer, "Compiler-Directed Dynamic Voltage Scaling for Memory-Bound Applications," Rutgers University Technical Report DCS-TR498, August 2002.

      5.  Min Yeol Lim, Vincent W. Freeh, and David K. Lowenthal. "Adaptive, Transparent Frequency and Voltage Scaling of Communication Phases in MPI Programs," IEEE/ACM Supercomputing 2006 (SC '06), November 2006.

      6.  Rob Springer, David K. Lowenthal, Barry Rountree, and Vincent W. Freeh. "Minimizing Execution Time in MPI Programs on an Energy-Constrained, Power-Scalable Cluster." 11th ACM Symposium on Principles and Practice of Parallel Programming (PPOPP), March 2006.

***7.  Nandani Kappiah, Vincent W. Freeh, and David K. Lowenthal. "Just In Time Dynamic Voltage Scaling: Exploiting Inter-Node Slack to Save Energy in MPI Programs." IEEE/ACM Supercomputing 2005 (SC '05), November 2005.

      8.  Vincent W. Freeh, Feng Pan, David K. Lowenthal, and Nandani Kappiah. "Using Multiple Energy Gears in MPI Programs on a Power-Scalable Cluster." 10th ACM Symposium on Principles and Practice of Parallel Programming (PPOPP), June 2005.

      9.  Vincent W. Freeh, David K. Lowenthal, Robert Springer, Feng Pan, and Nandani Kappiah. "Exploring the Energy-Time Tradeoff in MPI Programs."19th IEEE/ACM International Parallel and Distributed Processing Symposium (IPDPS), April 2005.

      10. Guilin Chen, Konrad Malkowski, Mahmut Kandemir, and Padma Raghavan, "Reducing Power with Performance Constraints for Parallel Sparse Applications," The first workshop on High-Performance, Power-Aware Computing, April 2005

***11. E. Pinheiro, R. Bianchini, and C. Dubnicki. "Exploiting Redundancy to Conserve Energy in Storage Systems". Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), June 2006.

***12. R. Bianchini and R. Rajamony. "Power and Energy Management for Server Systems". IEEE Computer, volume 37, number 11, November 2004. Special issue on Internet data centers.

      13. T. Heath, E. Pinheiro, J. Hom, U. Kremer, and R. Bianchini. "Code Transformations for Energy-Efficient Device Management". IEEE Transactions on Computers, volume 53, number 8, August 2004.

      14. E. Pinheiro, R. Bianchini, E. V. Carrera, and T. Heath. "Dynamic Cluster Reconfiguration for Power and Performance". Compilers and Operating Systems for Low Power, Luca Benini, Mahmut Kandemir, and J. Ramanujam (eds.), Kluwer Academic Publishers, September 2003.

      15. T. Heath, E. Pinheiro, J. Hom, U. Kremer, and R. Bianchini. "Application Transformations for Energy and Performance-Aware Device Management". Proceedings of the 11th International Conference on Parallel Architectures and Compilation Techniques, September 2002.

      16. J. Hom and U. Kremer, "Inter-program Compilation for Disk Energy Reduction," Workshop on Power-Aware Computer Systems (PACS'03), San Diego, CA, December 2003, LNCS 3164, Springer Verlag.

      17. T. Heath, E. Pinheiro, J. Hom, U. Kremer, and R. Bianchini, "Code Transformations for Energy-Efficient Device Management," IEEE Transactions on Computers 53(8), August 2004.

***18. Vivek Pandey, Weihang Jiang, Yuanyuan Zhou and Ricardo Bianchini. DMA-aware memory energy management for data servers. The Proceedings of the 10th International Symposium on High-Performance Computer Architecture (HPCA'06) ,  Feb 2006.

      19. Qingbo Zhu, Zhifeng Chen, Lin Tan, Yuanyuan Zhou, Kimberley Keeton and John Wilkes. Hibernator: Helping disk array sleep through the winter. In proceedings of the 20th ACM Symposium on Operating Systems Principles (SOSP'05), October 2005.

      20. Xiaodong Li, Zhenmin Li, Yuanyuan Zhou and Sarita Adve . Performance-directed energy management for Storage. ACM Transactions on Storage (ACM-TOS), 2005

      21. Qingbo Zhu and Yuanyuan Zhou. Power Aware Storage Cache Management.  IEEE Transactions on Computers (IEEE-TC), p598-602, Vol. 54, No. 5, May, 2005.

      22. J. Koomey, “Sorry, Wrong Number: How to separate fact from fiction in the Information Age” , IEEE Spectrum, pp11-12, June 2003.

      23. C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. Keller, "Energy Management for Commercial Servers," IEEE Computer, 36 (12), pp. 39-48, 2003.

    Performance Modeling, Analysis, and Evaluation

      1.  Robert D. Silverman, ‘‘Exposing the Mythical MIPS Year,’’ IEEE Computer, Vol. 32, No. 8, August 1999, pp. 22-26.

      2.  P. J. Fleming and J. J. Wallace, "How Not To Lie With Statistics: The Correct Way To Summarize Benchmark Results," Comm. ACM, Vol. 29, No. 3, March 1986, pp. 218-221.

***3.  James E. Smith, "Characterizing Computer Performance with a Single Number," Comm. ACM, October 1988, pp. 1202-1206.

      4.  James R. Larus, "Efficient Program Tracing," IEEE Computer, Vol. 26, No. 5, May 1993, pp. 52-61.

      5.  Rafael H. Saavedra, R. Stockton Gaines, and Michael J. Carlton, "Characterizing the Performance Space of Shared-Memory Computers Using Micro-Benchmarks," University of Southern California Department of Computer Science Technical Report no. USC-CS-93-547 (http://www.usc.edu/dept/cs/tech.html).

      6.  John L. Henning, "SPEC CPU2000: Measuring CPU Performance in the NewMillennium," IEEE Computer, Vol. 33, No. 7, July 2000, pp. 28-35.

      7.  Ran Giladi and Niv Ahituv, "SPEC as a Performance Evaluation Measure," IEEE Computer, Vol. 28, No. 8, August 1995, pp. 33-42.

      8.  George Marsaglia, "Technical Correspondence: Remarks on Choosing and Implementing Random Number Generators," Communications of the ACM, Vol. 36, No. 7, July 1993, pp. 105-110.

      9.  L. Gong, X.H. Sun, and E. Waston, "Performance Modeling and Prediction of Non-Dedicated Network Computing", IEEE Trans. on Computers, Vol 51, No 9, pp. 1041-1055, September, 2002.

      10. Z. Zhang and X. Zhang, ``Fast bit-reversals on uniprocessors and shared-memory multiprocessors", SIAM Journal on Scientific Computing, Vol. 22, No. 6, 2001.

      11. L. Xiao, X. Zhang, and S. Kubricht, ``Improving memory performance of sorting algorithms", ACM Journal on Experimental Algorithmics, Vol. 5, 2000.

      12. Z. Zhu and X. Zhang, ``Access-mode predictions for low-power cache design", IEEE Micro, Vol. 22, No. 2, March/April, 2002, pp. 58-71

      13. Z. Zhang, Z. Zhu, and X. Zhang, ``A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality", Proceedings of the 33rd Annual International Symposium on Microarchitecture, (Micro-33), Monterey, California, December 10-13, 2000. pp. 32-41

      14. Z. Zhu, Z. Zhang, and X. Zhang, ``Fine-grain priority scheduling on multi-channel memory systems", Proceedings of the 8th International Symposium on High Performance Computer Architecture, (HPCA-8), Cambridge, Massachusetts, February 2-6, 2002, pp. 107-116.

      15. S. Jiang and X. Zhang, ``LIRS: an efficient low inter-reference recency set replacement to improve buffer cache performance", Proceedings of the 2002 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'02), Marina Del Rey, California, June 15-19, 2002.

      16. D. W. Wall, "Limits of instruction-level parallelism," proceedings of 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp 176-189 Santa Clara, CA, 1991.

      17. L. G. Valiant, "A Bridging Model for Parallel Computation," Communications of the ACM 33(8), pp 103-111, August, 1990.

***18. D. E. Culler, R. M. Karp, D. Patterson, A. Sahay, E. E. Santos, K. E. Schauser, R. Subramonian, and T. von Eicken, "A Practical Model of Parallel Computation," Communications of the ACM 39(11), pp 78-85, November 1996.

***19. J. Gustafason, "Reevaluate Amdahl's law, " CACM vol 31, 1988. 

***20. X-H. Sun, "Scalable Problems and Memory Bounded Speedup," Journal of Parallel and Distributed Computing 19(1), pp 27-37, 1993.

Strongly recommended reading materials for SCAPE new members

The following list only serves to introduce you basic skills and tools. It is neither complete nor thorough. The complete list depends on your own exploring. 

System and administration

Performance evaluation tools

Performance benchmarks

Power-aware techniques

Major Conferences

Name
Long Name
Date
Place
Abstract Due
Paper Due
PPoPP Principles and Practice of Parallel Programming March 14, 2007 an Jose, USA   Sept 15, 2006
IPDPS '21 IEEE International Parallel & Distributed Processing Symposium Mar 26, 2007 Long Beach, CA -- Oct 09, 2006
SIGMETRICS International Conference on Measurement and Modeling of Computer Systems Jun 12,  2007 San Diego, CA Oct 27, 2006 Nov 03, 2006
ISCA International Symposium of Computer Architecture        
Euro-Par European Conference on Parallel Computing        
ICS International Conference on Supercomputing        
ASPLOS Architectural Support for Programming Languages and Operating Systems        
SC High Performance Computing, Networking and Storage Conference (SuperComputing)        
HPCA International Symposium on High-Performance Computer Architecture        
ICPP Intl Conf on Parallel Processing        
HPCN High-Performance Computing and Networking        
PADS ACM/IEEE/SCS Workshop on Parallel \& Dist Simulation        
HPPAC High-Performance Power-Aware Computing        
PACT Parallel Architecture and Compilation Techniques