Xun (Steve) Jian
Assistant Professor at Virginia Tech CS
About Me: I obtained my PhD in Computer Engineering from University of Illinois at Urbana Champaign in Fall, 2017. My primary research is computer architecture, with special interest in memory architectures, high-performance architectures, energy-efficient architectures, reliable and secure architectures.
HEAP (High-performance, Energy-efficient, Assured Processing) Lab
- Da Zhang
- Muhammad Laghari
- Xin Wang
- Daulet Talapkaliyev
- Gagandeep Panwar
- Niti Sharma
- Yamini Gaur
- Guohui Lee
- Jon Marks
- Yuqing Liu
- Kate Nguyen: M.S. 2018. First job: Software security consultant at Federal Reserve System
- Kehan Lyu: B.S. 2018. VT CS Best Undergraduate Researcher of the Year in 2018. Next step: Duke CS graduate program
- Xianze Meng: B.S. 2018. Present at ISCA as an undergrad. Next step: UCSD CSE graduate program
Da Zhang, Vilas Sridharan, and Xun Jian. “Exploring and Optimizing Chipkill-correct for Persistent Memory Based on High-density NVRAMs," in Proceedings of the 51st International Symposium on Microarchitecture (MICRO), October 2018.
Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, and Xun Jian. “Nonblocking Memory Refresh,” in Proceedings of the 45th International Symposium on Computer Architecture (ISCA), June 2018. (PDF)
Prior to 2018
Xun Jian, Pavan Hanumolu, and Rakesh Kumar. “Understanding and Optimizing Power Consumption in Memory Networks,” High Performance Computer Architecture (HPCA), 2017.
Henry Duwe, Xun Jian, Daniel Petrisko, and Rakesh Kumar. “Transforming Error Patterns to Enable Deeper Voltage Scaling in On-chip Memories,” International Symposium on Computer Architecture (ISCA), 2016.
Xun Jian, Vilas Sridharan, and Rakesh Kumar. “Parity Helix: Efficient Protection against Single-Dimensional Faults in Multi-dimensional Memory Systems,” High Performance Computer Architecture (HPCA), 2016.
Henry Duwe, Xun Jian, and Rakesh Kumar. “Correction Prediction: Reducing Strong Error Correction Latency for Low Vmin On-chip Caches,” High Performance Computer Architecture (HPCA), 2015.
Xun Jian and Rakesh Kumar. “ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems,” The International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2014.
Xun Jian, Henry Duwe, John Sartori, Vilas Sridharan, and Rakesh Kumar. “Low-power, low-storage-overhead Chipkill Correct via Multi-line Error Correction,” The International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2013.
Xun Jian and Rakesh Kumar, “Adaptive Reliability Chipkill Correct,” High Performance Computer Architecture (HPCA), 2013.
- CS2506:Computer Organizations II (Fall, 2017)
- CS5504:Advanced Computer Architecture (Spring, 2018)
Services: Conferences:HPCA'18,ICS'18,DFTS'18,HPCA'19. Journals:TC'18,JSA'18,ICAS-II'18