Xun (Steve) Jian



xunj@vt.edu
Assistant Professor at Virginia Tech CS

About Me: I obtained my PhD in Computer Engineering from University of Illinois at Urbana Champaign in Summer of 2017. My primary research is computer architecture, with special interest in memory architectures, high-performance architectures, energy-efficient architectures, reliable and secure architectures.

HEAP (High-performance, Energy-efficient, Assured Processing) Lab

      PhD Students:
      Masters Students:
      Undergraduate Students:
      Masters Alumni:
      Undergraduate Alumni:

Research Highlights

(*People who are/were part of HEAP LAB)

In 2021

  • Da Zhang*, Gagandeep Panwar*, Jagadish Kotra (AMD Research), Nathan DeBardeleben (Los Alamos National Laboratory), Sean Blanchard (Los Alamos National Laboratory), Xun Jian*, "Quantifying Server Memory Frequency Margin and Using it to Improve Performance in HPC Systems," to appear in the Proceedings of the 48th Annual International Symposium on Computer Architecture (ISCA), June 2021. (PDF)(Acceptance rate: 76/406=19%)

  • In 2020

  • NSF SHF:CAREER Award ($517K, sole PI). Thanks NSF!
  • A research grant from Los Alamos National Lab (LANL) ($100K, sole PI). Thanks LANL!
  • Harrison Williams(VT), Xun Jian*, and Matthew Hicks(VT), "Forget Failure: Exploiting SRAM Data Remanence for Low-overhead Intermittent Computation," in the Proceedings of the Twenty-fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020.(Acceptance rate: 86/479=18%)

  • In 2019

  • Gagandeep Panwar*, Da Zhang*, Yihan Pang(VT), Mai Dahshan(VT), Nathan Debardeleben(LANL), Binoy Ravindran(VT), and Xun Jian*. “Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support,” in Proceedings of the 52nd International Symposium on Microarchitecture (MICRO), October 2019. (PDF)(Acceptance rate: 79/344=22.9%)
  • NSF SPX grant ($950K, 25% credit, co-PI). Thanks NSF!
  • CRII:SHF award ($180K, sole PI). Thanks NSF!
  • Kate Nguyen*, Kehan Lyu*, Xianze Meng*, Vilas Sridharan(AMD), and Xun Jian*. “Nonblocking DRAM Refresh,” IEEE Micro Journal: Top Picks Issue, May 2019 (PDF)(Acceptance rate: 12/123=9.8%; effective acceptance rate:<2%, as the 123 submissions were based on papers from top-tier conferences with ~20% acceptance rate).

  • In 2018

  • Da Zhang*, Vilas Sridharan(AMD), and Xun Jian*. “Exploring and Optimizing Chipkill-correct for Persistent Memory Based on High-density NVRAMs," in Proceedings of the 51st International Symposium on Microarchitecture (MICRO), October 2018. (PDF) (Acceptance rate: 74/351=21.1%)
  • Kate Nguyen*, Kehan Lyu*, Xianze Meng*, Vilas Sridharan(AMD), and Xun Jian*. “Nonblocking Memory Refresh,” in Proceedings of the 45th International Symposium on Computer Architecture (ISCA), June 2018. (PDF) (Acceptance rate: 64/378=17.0%)

  • 2017 and earlier

  • Xun Jian, Pavan Hanumolu, and Rakesh Kumar. “Understanding and Optimizing Power Consumption in Memory Networks,” High Performance Computer Architecture (HPCA), 2017.
  • Henry Duwe, Xun Jian, Daniel Petrisko, and Rakesh Kumar. “Transforming Error Patterns to Enable Deeper Voltage Scaling in On-chip Memories,” International Symposium on Computer Architecture (ISCA), 2016.
  • Xun Jian, Vilas Sridharan, and Rakesh Kumar. “Parity Helix: Efficient Protection against Single-Dimensional Faults in Multi-dimensional Memory Systems,” High Performance Computer Architecture (HPCA), 2016.
  • Henry Duwe, Xun Jian, and Rakesh Kumar. “Correction Prediction: Reducing Strong Error Correction Latency for Low Vmin On-chip Caches,” High Performance Computer Architecture (HPCA), 2015.
  • Xun Jian and Rakesh Kumar. “ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems,” The International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2014.
  • Xun Jian, Henry Duwe, John Sartori, Vilas Sridharan, and Rakesh Kumar. “Low-power, low-storage-overhead Chipkill Correct via Multi-line Error Correction,” The International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2013.
  • Xun Jian and Rakesh Kumar, “Adaptive Reliability Chipkill Correct,” High Performance Computer Architecture (HPCA), 2013.

  • Professional Services

    Teaching