Xun (Steve) Jian
Assistant Professor at Virginia Tech CS
About Me: I obtained my PhD in Computer Engineering from University of Illinois at Urbana Champaign in Summer of 2017. My primary research is computer architecture, with special interest in memory architectures, high-performance architectures, energy-efficient architectures, reliable and secure architectures.
HEAP (High-performance, Energy-efficient, Assured Processing) Lab
- Kate Nguyen: M.S. 2018. Next step: Software security consultant at Federal Reserve System
- Niti Sharma: M.S. 2019. Next step: Paypal
- Yamini Gaur: M.S. 2019. Next step: Citrix
- Daulet Talapkaliyev: M.S. 2019. Next step: Juniper Networks
- Varun Kumthekar: Meng 2019. Next step: Intel
- Raghavendra Srinivas: M.S. 2020. Next step: Apple
- Chandler Jearls: M.S. 2021. Next step: Apple
- Kehan Lyu: B.S. 2018. VT CS Best Undergraduate Researcher of the Year in 2018. Next step: Duke CS graduate program
- Xianze Meng: B.S. 2018. Presented at ISCA as an undergrad. Next step: UCSD CSE graduate program
- Jon Marks: B.S. 2019. Next step: Google
- Yuzhi Ma: B.S. 2021. Next step: CMU CS graduate program
- David Bears: B.S. 2021. Next step: Georgia Tech PhD program
External Research Funding
Google Research Scholar Award, 2022 ($60000, sole PI). Thanks Google!
NSF SHF:CAREER Award, 2020 ($517K, sole PI). Thanks NSF!
A research grant from Los Alamos National Lab (LANL), 2020 ($100K, sole PI). Thanks LANL!
NSF SPX grant ($950K, 25% credit, co-PI), 2019. Thanks NSF!
CRII:SHF Award, 2019 ($180K, sole PI). Thanks NSF!
who are/were part of HEAP LAB)
Gagandeep Panwar*, Muhammad Laghari*, David Bears*, Yuqing Liu*, Chandler Jearls*, Esha Choukse (Microsoft), Kirk Cameron (VT), Ali Butt (VT), Xun Jian. Translation-optimized Memory Compression for Capacity, MICRO 2022. (PDF) (Acceptance rate: 83/369=22%)
Xin Wang*, Jagadish Kotra (AMD), Xun Jian. Eager Memory Cryptography in Caches, MICRO 2022. (PDF)(Acceptance rate: 22%)
Xin Wang*, Daulet Talapkaliyev*, Matthew Hicks (VT), Xun Jian. Self-Reinforcing Memoization for Cryptography Calculations in Secure Memory Systems, MICRO 2022. (PDF)(Acceptance rate: 22%)
Da Zhang*, Gagandeep Panwar*, Jagadish Kotra (AMD Research), Nathan DeBardeleben (LANL), Sean Blanchard (LANL), Xun Jian. Quantifying Server Memory Frequency Margin and Using it to Improve Performance in HPC Systems, ISCA 2021. (PDF)(Acceptance rate: 76/406=19%)
Harrison Williams (VT), Xun Jian, and Matthew Hicks (VT). Forget Failure: Exploiting SRAM Data Remanence for Low-overhead Intermittent Computation, ASPLOS 2020.(Acceptance rate: 86/479=18%)
Gagandeep Panwar*, Da Zhang*, Yihan Pang (VT), Mai Dahshan (VT), Nathan Debardeleben (LANL), Binoy Ravindran (VT), and Xun Jian. Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support, MICRO 2019. (PDF)(Acceptance rate: 79/344=22.9%)
Kate Nguyen*, Kehan Lyu*, Xianze Meng*, Vilas Sridharan(AMD), and Xun Jian. “Nonblocking DRAM Refresh,” IEEE Micro Journal: Top Picks Issue, 2019 (PDF)(Acceptance rate: 12/123=9.8%; effective acceptance rate:<2%, as the 123 submissions were based on papers from top-tier conferences with ~20% acceptance rate).
Da Zhang*, Vilas Sridharan(AMD), and Xun Jian. Exploring and Optimizing Chipkill-correct for Persistent Memory Based on High-density NVRAMs, MICRO 2018. (PDF) (Acceptance rate: 74/351=21.1%)
Kate Nguyen*, Kehan Lyu*, Xianze Meng*, Vilas Sridharan(AMD), and Xun Jian. Nonblocking Memory Refresh, ISCA 2018. (PDF) (Acceptance rate: 64/378=17.0%)
2017 and earlier
Xun Jian, Pavan Hanumolu, and Rakesh Kumar. “Understanding and Optimizing Power Consumption in Memory Networks,” HPCA, 2017.
Henry Duwe, Xun Jian, Daniel Petrisko, and Rakesh Kumar. “Transforming Error Patterns to Enable Deeper Voltage Scaling in On-chip Memories,” ISCA, 2016.
Xun Jian, Vilas Sridharan, and Rakesh Kumar. “Parity Helix: Efficient Protection against Single-Dimensional Faults in Multi-dimensional Memory Systems,” HPCA, 2016.
Henry Duwe, Xun Jian, and Rakesh Kumar. “Correction Prediction: Reducing Strong Error Correction Latency for Low Vmin On-chip Caches,” HPCA, 2015.
Xun Jian and Rakesh Kumar. “ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems,” The International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2014.
Xun Jian, Henry Duwe, John Sartori, Vilas Sridharan, and Rakesh Kumar. Low-power, low-storage-overhead Chipkill Correct via Multi-line Error Correction, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2013.
Xun Jian and Rakesh Kumar, Adaptive Reliability Chipkill Correct, HPCA, 2013.
- Program committee member at HPCA'22, ICCD'22, ICCD'21, DFTS'20, ISCA'19, DFTS'19, DFTS'18
- External reviewer for MICRO'22, MICRO'21, ISCA'21, HPCA'21, ASPLOS'21, MICRO'20, ISCA'20, HPCA'19, HPCA'18, ICS'18
- Reviewed journal article for TC'20, JDPC'19, CAL'19/'18, TC'18, JSA'18
- CS2506:Computer Organization II (Fall, 2017)
- CS5504:Advanced Computer Architecture (Spring, 2018)
- CS2506:Computer Organization II (Spring, 2019)
- CS2506:Computer Organization II (Fall, 2019)
- CS6504:Memory System Architecture (Spring, 2020)
- CS2506:Computer Organization II (Fall, 2020)