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When an operation traps, the conceptual model is that everything stops and
the trap handler is executed; since the underlying assumption is that of
serial execution, traps are harder to implement on machines that use pipelining
or have multiple ALU. Hardware support for identifying exactly
which operation did trap may be needed. For example,
both operations can be physically executed in parallel;
if the multiplication traps, the handler will need the value of
the arguments y and z. But the value of z is modified by the
addition, which started in the same time as the multiply and eventually finished
first. IEEE supporting systems must either avoid such a situation, or provide a
way to store z and pass the original value to the handler, if needed.