Wu-chun Feng

Wu-chun Feng (a.k.a. "Wu")

Director
SyNeRGy Laboratory

Professor
Dept. of CS
Dept. of ECE
Health Sciences

Other Affiliations
CHREC | VBI |
Wireless @ VT

Profiles
Google Scholar

Contact

Office:
Torgersen Hall 2050
620 Drillfield Drive (Alumni Mall)
Blacksburg, VA.
24061. [map]
Phone:
(540) 231-1192
Fax:
(540) 231-9218
Email:
feng [at] cs.vt.edu

Virginia Tech

News

  • ( 05/21/18 )
    End of Tour Award Winner
    Congratulations to Ahmed Helal for being selected as one of three worldwide winners of the “End of Tour Award” for the spring at AMD!

  • ( 05/14/18 )
    Paper Accepted to ICPP 2018
    Krommydas, Sathre, and Feng, in collaboration with Sasanka of Intel, have their paper — A Framework for Auto-Parallelization and Code Generation: An Integrative Case Study with Legacy FORTRAN Codes — accepted for publication at the 47th International Conference on Parallel Processing to be held in Eugene, OR in August 2018.

  • ( 04/24/18 )
    Paper Accepted to ACM HPDC 2018
    Helal, Jung, Hanafy, and Feng have their paper — Automated Estimation of Communication Cost and Scalability on HPC Clusters from Sequential Code — accepted for publication in the 27th International ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC) to be held in Tempe, Arizona in June 2018.

  • ( 03/09/18 )
    Papers Accepted to ACM CF 2018
    Zhang, Wang, and Feng, in collaboration with Aji and Chu of AMD, have their paper — Taming Irregular Applications via Dynamic Parallelism: How Far Have We Come? — accepted for publication in the 15th ACM International Conference on Computing Frontiers (CF’18) to be held in Ischia, Italy, May 2018. Likewise, Dutta, Adhinarayanan, and Feng, have their paper — GPU Power Prediction via Ensemble Machine Learning for DVFS Space Exploration — accepted for publication in the 15th ACM International Conference on Computing Frontiers (CF’18) to be held in Ischia, Italy, May 2018.

  • ( 03/06/18 )
    Paper Accepted to HPPAC 2018
    Adhinarayanan, Dutta, and Feng, have their paper — Making a Case for Green High-Performance Visualization via Embedded Graphics Processors — accepted for publication in the 14th Workshop on High-Performance, Power-Aware Computing (HPPAC'18) to be held in conjunction with the 32nd IEEE International Parallel and Distributed Processing Symposium in Vancouver, British Columbia, Canada, May 2018.

  • ( 02/09/18 )
    MS Graduate from the Synergy Lab
    Congratulations to Anshuman Verma for receiving his MS degree for "On the Programmability and Performance of OpenCL designs for FPGA." Verma started in 2015 and finished his degree in 2017. Best wishes to him on his Hardware Engineer position at Microsoft!

  • ( 02/06/18 )
    MS Graduate from the Synergy Lab
    Congratulations to Bishwajit Dutta for receiving his MS degree for "Power Analysis and Prediction for Heterogeneous Computation." Best wishes to him on his Software Pathfinding Engineer position at Intel!

More ...